The present invention relates to a data transmission circuit of a dynamic random access memory (DRAM) in a semiconductor integrated circuit, and more particularly to the data transmission circuit capable of performing high-speed operation with a high degree of integration.
Recently, a need for both the large-scale integration of a semiconductor integrated circuit and the high-speed operation of a chip thereof has been developed. However, if the large-scale integration of the semiconductor integrated circuit is achieved, it is difficult for the chip to operate at high speed, and if the high-speed operation of the chip is achieved, it is difficult to realize the semiconductor circuit having a high degree of integration. Therefore the simultaneous achievement of the high-speed operation and high integrated degree is one of the problems to be solved in the field of the semiconductor integrated circuit. In particular, it is a well known fact that, in a data transmission circuit directly related to the high-speed operation and the high integration, the improved construction method of the data transmission circuit and the enhanced device of each element therein should be contrived, in order to provide a semiconductor integrated circuit with a higher integrated degree and a higher operating speed than present.
FIG. 1 shows a schematic diagram of a conventional data transmission circuit, and FIG. 2 shows a timing chart during the read operation of FIG. 1. The circuit of FIG. 1 is comprised of memory cells 9 and 10, word lines 11 and 12, bit lines 15 and 16, a sense amplifier 7 for sensing the bit lines 15 and 16, isolation transistors 1, 2, 3 and 4 for isolating the memory cells 9 and 10, respectively, input/output transistors 5 and 6, each having a channel, one terminal of each channel being connected to the bit lines 15 and 16, respectively, common input/output lines 13 and 14 connected to the other terminal of the channel of the input/output transistors 5 and 6, respectively, and an input/output line sense amplifier 8 for sensing the common input/output lines 13 and 14.
The operation of FIG. 1 is described in conjunction with FIG. 2. When reading out the data stored in the memory cell 9, the isolation transistors 1 and 2 connected to the memory cell 9 are turned on, and the isolation transistors 3 and 4 are turned off. Moreover, the word line 11 of the memory cell 9 is selected so that the data of the memory cell 9 is transferred to the bit line 15. Thus, the potential of the bit lines 15 and 16 is different, and the potential difference between the bit lines 15 and 16 is amplified through the sense amplifier 7. Thereafter, data of the bit lines 15 and 16 is transferred to the input/output lines 13 and 14 through the input/output transistors 5 and 6 if a column selection line CSL signal of logic "high" is applied to the gates of the input/output transistors 5 and 6. The potential difference of data in the input/output lines 13 and 14, which is pulled down by the parasitic capacitance of the input/output lines 13 and 14, is amplified through the input/output sense amplifier 8. The main feature of this data transmission circuit lies in that the bit lines 15 and 16 and the input/output lines 13 and 14 are connected to the source and drain of the input/output transistors 5 and 6. Accordingly, since the column selection line CSL signal must be selected after the potential difference of the bit lines 15 and 16 is sufficiently amplified, there occurs the decrease of the output speed caused by the delay time of the column select line CSL line. Namely, as shown in FIG. 2, when the potential difference .DELTA.V.sub.BL of the bit lines BL and BL is approximately 1V, the column selection line CSL signal is enabled as a logic "high" level. Furthermore, since the data transferred to the input/output lines 13 and 14 pass through the input/output transistors 5 and 6, a voltage drop as much as the threshold voltage of the input/output transistors 5 and 6, is generated. In addition, when the input/output transistors 5 and 6 are turned on, since the input/output lines 13 and 14 and the bit lines 15 and 16 are connected to the input/output transistors 5 and 6, the parasitic capacitance is amplified, and the potential difference of the data transferred to the input/output lines 13 and 14 is further decreased. As a result, the sensing capability of the input/output line sense amplifier 8 is deteriorated.
FIG. 3 shows a schematic diagram of another conventional data transmission circuit. The circuit is disclosed in "1991 Symposium on VLSI (very large scale integration) Circuit", Texas Instruments, Inc., a paper on 64 mega DRAM. The feature of the circuit in FIG. 3 lies in the fact that the data of a memory cell 20 is not directly transferred to data input/output lines 37 and 38, but transferred to the gates of output transistors 27 and 28. As a result, the transfer speed of the data becomes faster, and the decrease of a potential caused by the loading of bit lines 21 and 22 is not generated.
The data transmission circuit of FIG. 3 includes the memory cell 20, first isolation transistors 23 and 24, bit lines 21 and 22, a bit line sense amplifier 25, sub input/output lines 33 and 34, second isolation transistors 31 and. 32 for isolating or connecting the bit lines 21 and 22 and sub input/output lines 33 and 34, a ground transistor 26, output transistors 27 and 28, input transistors 29 and 30, transfer transistors 35 and 36, data input/output lines 37 and 38, and an input/output line sense amplifier 39 for sensing the potential difference between data input/output lines 37 and 38.
A memory array element 40 shown in dotted line is a part of a given memory array block, which is shown in detail in FIG. 4. Referring to FIG. 4, it will be appreciated why the second isolation transistors 31 and 32 of FIG. 3 are constituted in such a manner. Namely, in the memory array block in FIG. 4, a plurality of memory cells exist and each bit line is connected to each memory cell. Therefore, only control of the second isolation transistors is needed in order to select a given bit line among these bit lines.
With reference to FIG. 5, illustrating a timing chart of FIG. 3 during the read operation, the operating characteristic of FIG. 3 will be described in detail. In this case, it should be noted that since the output transistors 27 and 28 for reading and input transistors 29 and 30 for writing, are separately constructed, a read column selection line RCSL signal and a write column selection line WCSL signal, for respectively controlling the above transistors, are separately applied. The reading operation of the data of the memory cell 20 is as follows. The first isolation transistors 23 and 24 are turned on, and the data of the memory cell 20 is transferred to the bit line 21. Thus the potential difference between the bit lines 21 and 22 is amplified by the sense amplifier 25. If the second isolation transistors 31 and 32 are turned on, the data is transferred to the sub input/output lines 33 and 34, and further is transferred to the gates of the output transistors 27 and 28. At this time, if the read column selection line RCSL signal is selected, the ground transistor 26 is turned on and the output transistors 27 and 28 come to serve as a sense amplifier. In other words, for example, if the data of the memory cell 20 is logic "1", the output transistor 27 is turned on and the output transistor 28 is turned off. In this case, if the transfer transistors 35 and 36 are turned on, the potential of the data input/output line 37 becomes a ground voltage level. Similarly, it will be readily appreciated that if the data of the memory cell 20 is logic "0", the potential of the data input/output line 38 becomes the ground voltage level. Accordingly the data of the input/output lines 37 and 38 are transferred to the exterior of a chip through the input/output sense amplifier 39. That is, the data of the memory cell 20 is read out.
Meanwhile, so as to write the data into the memory cell 20 after the given data is transferred up to the data input/output lines 37 and 38, firstly the transfer transistors 35 and 36 should be turned on. If the write column selection line WCSL signal is selected and the input transistors 29 and 30 are turned on, the data of the input/output lines 37 and 38 are transferred to the sub input/output lines 33 and 34. If the second isolation transistors 31 and 32 are turned on, the data is transferred to the bit lines 21 and 22, and the potential difference of the data is amplified at the bit line sense amplifier 25. Thereafter, the data is stored into the memory cell 20 through the first isolation transistors 23 and 24.
In the data transmission circuit shown in FIG. 3, since the sub input/output lines 33 and 34, transferring the potential of the bit lines 21 and 22 to the data input/output lines 37 and 38, are connected directly to the gates of the output transistors 27 and 28, the output speed of the data is improved in comparison with the circuit of FIG. 1. However, during the read and write operation, a voltage drop is generated. In more detail, during the read operation, since, in order to transfer data to the data input/output lines 37 and 38, the data of the bit lines 21 and 22 must pass through two NMOS transistors 31 and 35, and 32 and 36, respectively, and a voltage drop as much as 2V.sub.TH (wherein V.sub.TH is the threshold voltage of an NMOS transistor) is generated. This leads to a delay of the switching time point during the complementary switching operation of the output transistors 27 and 28. That is, as shown in FIG. 5, even if a signal .THETA.SAE is enabled as a power voltage V.sub.CC level, thereby turning on the second isolation transistors 31 and 32, since the potential difference between the sub input/output lines 33 and 34 is increased after the potential of the bit lines 21 and 22 is sufficiently amplified at the bit line sense amplifier 25, the enable time point of the read column selection line RCSL signal is delayed. Consequently, the speed of the data access time becomes slower. Furthermore, during the write operation, since, in order to transfer the given data of the data input/output lines 37 and 38 to the bit lines 21 and 22, the data must pass through three NMOS transistors 35, 29 and 31, and 36, 30 and 32, respectively, and a voltage drop as much as 3V.sub.TH is generated.
To prevent the above problems, in the circuit shown in FIG. 3, the voltage applied to the gates of the first isolation transistors 23 and 24, the second isolation transistors 31 and 32 and the transfer transistors 35 and 36, should be higher than the power voltage V.sub.CC, and a predetermined bootstrap circuit (not shown) is necessitated. However, since this leads to the deterioration of the high integration, the application of a future VLSI semiconductor memory device, is difficult.